IC Knowledge

Introduction
The IC Knowledge - IC Cost Model is designed to enable users to easily estimate manufacturing costs for most IC's. The cost model runs inside of Excel, the user makes selections from drop-down menus on 2 worksheets covering wafer and product cost. The user must make 8 selections many of which have lookup help available, there are 66 additional selections available on the default sheet that may be overriden if desired to fine tune the model and the process may now be fined tuned to add and subtract individual process steps. All of the defaults are technology specific and in most cases will not need to be changed. There are 8 output sheets that provide a detailed breakout of costs. The model also includes a calculator for stacked die - multi-chip packages.

Who should buy this product
This product is designed to serve the needs of anyone interested in understanding the manufacturing costs of integrated circuits and who also wants detail on the wafer fabrication costs section.

Do you:

Purchase ICs and want to know what it really costs your supplier to make the ICs?
Market ICs and want to know what your competitors products cost?
Market equipment and want to understand how equipment costs impact IC costs?
Manage an IC manufacturing operation and want to benchmark your company against others?
Follow IC companies stocks and want to know what particular products cost them to make?
Develop new products and want to understand the cost impact of process decisions.
Work at a Fabless IC company and want to know what it costs your suppliers to make wafers for you?

If you answered yes to any of the question above, then this product is for you.

What is different for 2010 versus the 2009 model
For the 2010 model all of the underlying model data has been reviewed and in many cases updated. The 2010 model also has several new processes more new processes planned to be added as the year progresses.

How to get more information about the model
We provide several tools to better understand the model before purchasing it.

Email us to get a demo copy of the model.
Applications notes detail the processes and packages supported, there are also several applications notes from the 2001 and 2002 models that although the model has changed and they don't specifically apply are still useful in a general sense. Application notes may be down loaded from the support page.
Process and package type lists.

If none of these tools answers your questions, please feel free to E-mail us at info@icknowledge.com

Revision history
The following is the revision history for the 2009 IC Cost Model:

Revision 1000 - added SMIC 350nm, 250nm, 180nm, 130nm and 90nm processes. Updated UMC, TSMC, SMIC, Tower, ASMC and Chartered gross margins. Updated 110nm mid lithography photoresist type. Updated OEE and other productivity factors. Adjusted labor productivity values for all 200mm memory processes. Adjusted mask usage factors. Adjusted material costs. Updated default test utilization and uptime percentages. Updated labor factors for test. Fixed a bug that caused foundry margins to display an error for the year 2000. Updated photoresist costs. Updated natural gas costs and fixed a bug in the 2015 natural gas cost calculation. Updated electric usage calculations. Adjusted labor productivity for Fabs in China. Adjusted 450mm toolset footprint, chemical and utility consumptions to equal 300mm per ISMI guidelines. Updated Intel defect densities for 65nm, 45nm and 32nm processes. Updated Intel 45nm, 32nm and 22nm processes and added 15nm process. Added 15nm Samsung NAND Flash process. Updated direct labor rates. Modified the model to add the years 2016 to 2020. Updated test factors to the latest ITRS guidelines. Modified depreciation calculations to allow for capacity expansion as well as upgrades. Modified depreciation calculation so there is always some minimum replacement depreciation level. Adjusted TSMC 150nm processes. Adjusted 300mm labor productivity. Updated Samsung common platform upgrades at 65nm and 45nm. Updated equipment capital costs for linewidths smaller than 350nm. Converted the Samsung 40nm NAND Flash process from TANOS to Floating Gate. Adjusted TI 300mm start-up dates and upgrades. Deleted Qimonda DRAM processes. Updated IDL rates. Updated TSMC 40nm defect densities. Added Chartered 150nm - 200mm and 300mm processes. Fixed an error in the defect denisty calculation. Changed upgrade tracking to be based on sepcific quarters instead of intervals and also to allow for expansions.
Revision 1000a - fixed an external link warning bug. Fixed a packaging layers cost calculation bug. Fixed a bug in the packaging heat pad calculation. Added TI 300mm - 65nm process.
Revision 1001 - added ASIC - High Performance - Ultra Complex product category. Added '8 Pricing' sheet and pricing calculations for foundry wafers and finished products. Updated 300mm starting wafer costs for 2008 to 2020. Adjusted DRAM product type names to make selection easier. Added die size for IM Flash 25nm NAND. Made improvements to the depreciation calculation. Revised Samsung and Toshiba 32nm NAND processes to a single SADP layer and 22nm to 3 SADP layers. Changed 15nm Samsung NAND process to 4 layers of QPS plus added EUV version. Updated the 15nm Intel process plus added EUV and QPS versions. Changed the default capacity setting to be the default initial capacity for the fab. Added a current capacity display on the defaults page that includes expansions.
Revision 1002 - added more gross margins to the '8 Price' page. Gross margins have been changed to reflect the average of the last five years if available. Fixed an error in the 300mm - 22nm - Intel labor productivity. Adjusted 450mm tool cost multipliers versus 300mm.
Revision 1003 - adjusted projected EUV mask costs. Updated packaging costs for 2010 and beyond. Added engineering wafers calculation to sheet '8 Pricing'. Fixed an error in one of the DSP sort test parameters. Fixed a bug in the test equipment year calculation. Added 48nm Samsung DRAM process. Added die sizes. Adjusted RF test times. Adjusted Samsung Fab expansions and upgrades. Adjusted Common Platform 45nm processes.
Revision 1004 - added 300mm - 65nm - TI - 7 layer copper process. Implemented a new test cost calculation algorithm. Updated test parallelism to the latest ITRS values. Adjusted UMC 200mm - 250nm Fab dates. Adjusted the 15nm EUV reticle costs. Adjusted 300mm raw wafer prices. Added a setting on the '4 Defaults' page to allow portions of an equipment set to have maintenance turned off during periods of low utilization. Adjusted natural gas usage. Adjusted electric and natural gas rates. Fixed an errors in the gross margins for SMIC and UMC. Updated the allowable range for foundry gross margins on the defaults page. Updated the '8 Price' page foundry gross margin calculations.
Revision 1005 - For Samsung DRAM on 300mm - added 150nm and 130nm, updated 90nm and 80nm, deleted 70nm and 65nm, added 68nm, updated 56nm and 48nm, added 39nm, 34nm, 29nm and 24nm. Added Samsung projected DRAM die sizes for 2Gb DDR3 at 39nm and 34nm and 4Gb DDR3 at 34nm, 29nm and 24nm. Changed mask usage default overide to support 1 to 100,000. Fixed a bug in the test algorithm that was in some cases overestimating wafer sort costs. For Samsung NAND on 300mm - updated 150nm, 120nm, 90nm, 73nm, 65nm, 51nm and 32nm. Added 42nm, 27nm, 23nm and 19nm. Change all 15nm processes to 16nm and updated them. Deleted Samsung 40nm NAND process. Added TSMC 300mm and 450mm 16nm processes. Changed Intel 15nm processes to 16nm and updated Intel 180nm, 130nm, 90nm, 65nm, 45nm, 32nm, 22nm and 16nm processes. Updated Global Foundries, IBM and TSMC 28nm processes and TSMC 22nm processes. Updated Toshiba 300mm NAND Flash processes at 90nm, 70nm, 56nm, 43nm and 32nm.
Revision 1006 - adjusted defect detection equipment footprint for 200mm and 300mm wafers. Fixed a bug in the 450mm - 24nm DRAM process equipment throughput. Updated foundry gross margins for TSMC and UMC so that each year is based on 90% utilization adjusted gross margin for the last 5 years (TSMC starts with 2005 and UMC with 2007). Changed the wording for selection 4 on the '2 Wafer cost' page. added 15 unlocked sheets, (30 through 44), a sheet listing the allowable selctions for the page 2 and 3 entries (page 50) and an unlocked override page (page 51). These added pages are to allow customers to add customization to the model. Added 450mm - TSMC - 22nm processes. Added total non-material (excludes starting and monitor wafers) cost and cost per square centimeter to the '16 Summary' page.
Revision 1007 - updated EUV throughput. Fixed a bug that effected 32nm reticle costs. Updated reticle costs for 500nm and smaller linewidths. Adjusted 22nm cirtical exposure tool cost. Added 32nm die sizes. Updated Intel 22nm and 16nm (DP) processes and Intel 16nm QPS processes. Added Numonyx 200mm - 65nm NOR Flash process. Added STMicro 300mm - 130nm CMOS Logic with Flash process.

Cost and how to buy

1st copy price - $1,700
2nd or 3rd copy price - $1,317
4th copy - $1,053
Enterprise license - $6,440

You can order on-line or we accept purchase orders from most companies.

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